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authorDave Airlie <airlied@redhat.com>2015-12-15 11:01:04 +1000
committerDave Airlie <airlied@redhat.com>2015-12-15 11:01:04 +1000
commit51bce5bc38bdb79c0f7ab33f1fe91a68ef1afa77 (patch)
treedaca655bba69a4a5fa1e11826c9e1cfed2280a4a /drivers/gpu/drm/i915/intel_crt.c
parentdrm/ttm: fix documentation of ttm_bo_reserve (diff)
parentdrm/i915: Update DRIVER_DATE to 20151204 (diff)
downloadlinux-dev-51bce5bc38bdb79c0f7ab33f1fe91a68ef1afa77.tar.xz
linux-dev-51bce5bc38bdb79c0f7ab33f1fe91a68ef1afa77.zip
Merge tag 'drm-intel-next-2015-12-04-1' of git://anongit.freedesktop.org/drm-intel into drm-next
This is the "fix igt basic test set issues" edition. - more PSR fixes from Rodrigo, getting closer - tons of fifo underrun fixes from Ville - runtime pm fixes from Imre, Daniel Stone - fix SDE interrupt handling properly (Jani Nikula) - hsw/bdw fdi modeset sequence fixes (Ville) - "don't register bad VGA connectors and fall over" fixes (Ville) - more fbc fixes from Paulo - and a grand total of exactly one feature item: Implement dma-buf/fence based cross-driver sync in the i915 pageflip path (Alex Goins) * tag 'drm-intel-next-2015-12-04-1' of git://anongit.freedesktop.org/drm-intel: (70 commits) drm/i915: Update DRIVER_DATE to 20151204 drm/i915/skl: Add SKL GT4 PCI IDs Revert "drm/i915: Extend LRC pinning to cover GPU context writeback" drm/i915: Correct the Ref clock value for BXT drm/i915: Restore skl_gt3 device info drm/i915: Fix RPS pointer passed from wait_ioctl to i915_wait_request Revert "drm/i915: Remove superfluous NULL check" drm/i915: Clean up device info structure definitions drm/i915: Remove superfluous NULL check drm/i915: Handle cdclk limits on broadwell. i915: wait for fence in prepare_plane_fb i915: wait for fence in mmio_flip_work_func drm/i915: Extend LRC pinning to cover GPU context writeback drm/i915/guc: Clean up locks in GuC drm/i915: only recompress FBC after flushing a drawing operation drm/i915: get rid of FBC {,de}activation messages drm/i915: kill fbc.uncompressed_size drm/i915: use a single intel_fbc_work struct drm/i915: check for FBC planes in the same place as the pipes drm/i915: alloc/free the FBC CFB during enable/disable ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c33
1 files changed, 27 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 912c0ac95f2a..9285fc1e64ee 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -777,11 +777,37 @@ void intel_crt_init(struct drm_device *dev)
struct intel_crt *crt;
struct intel_connector *intel_connector;
struct drm_i915_private *dev_priv = dev->dev_private;
+ i915_reg_t adpa_reg;
+ u32 adpa;
/* Skip machines without VGA that falsely report hotplug events */
if (dmi_check_system(intel_no_crt))
return;
+ if (HAS_PCH_SPLIT(dev))
+ adpa_reg = PCH_ADPA;
+ else if (IS_VALLEYVIEW(dev))
+ adpa_reg = VLV_ADPA;
+ else
+ adpa_reg = ADPA;
+
+ adpa = I915_READ(adpa_reg);
+ if ((adpa & ADPA_DAC_ENABLE) == 0) {
+ /*
+ * On some machines (some IVB at least) CRT can be
+ * fused off, but there's no known fuse bit to
+ * indicate that. On these machine the ADPA register
+ * works normally, except the DAC enable bit won't
+ * take. So the only way to tell is attempt to enable
+ * it and see what happens.
+ */
+ I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
+ ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
+ if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
+ return;
+ I915_WRITE(adpa_reg, adpa);
+ }
+
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
if (!crt)
return;
@@ -815,12 +841,7 @@ void intel_crt_init(struct drm_device *dev)
connector->interlace_allowed = 1;
connector->doublescan_allowed = 0;
- if (HAS_PCH_SPLIT(dev))
- crt->adpa_reg = PCH_ADPA;
- else if (IS_VALLEYVIEW(dev))
- crt->adpa_reg = VLV_ADPA;
- else
- crt->adpa_reg = ADPA;
+ crt->adpa_reg = adpa_reg;
crt->base.compute_config = intel_crt_compute_config;
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {