diff options
| author |   Imre Deak <imre.deak@intel.com> | 2018-06-13 20:27:46 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2018-06-14 19:50:07 +0300 |
| commit | afb2c4437daeed2d0c49e246ad1ad4def5d913cd (patch) | |
| tree | 8ab76421a00d800ce380d9e605a22f00c93134ee /drivers/gpu/drm/i915/intel_crt.c | |
| parent | drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable() (diff) | |
| download | linux-dev-afb2c4437daeed2d0c49e246ad1ad4def5d913cd.tar.xz linux-dev-afb2c4437daeed2d0c49e246ad1ad4def5d913cd.zip | |
drm/i915/ddi: Push pipe clock enabling to encoders
On ICL the pipe clock needs to be enabled before setting the HDMI
infoframe, but these steps are in the reverse order atm. Move the pipe
clock enabling to the encoders, so reordering of the two steps can be
done in a clean way.
No functional change.
v2:
- Rebased on drm-tip.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180613172746.18525-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 95aa29cf2d9c..87c72c39f409 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -232,6 +232,8 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + intel_ddi_disable_pipe_clock(old_crtc_state); + pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); lpt_disable_pch_transcoder(dev_priv); @@ -268,6 +270,8 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder, intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv->display.fdi_link_train(crtc, crtc_state); + + intel_ddi_enable_pipe_clock(crtc_state); } static void hsw_enable_crt(struct intel_encoder *encoder, |