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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-03-08 17:46:23 +0200
committerAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-03-09 11:55:31 +0200
commitdaedf20a4f69685a636c9104cf6f1f5d8835345b (patch)
treeb63a425c0537213fd22da74466f6a8f650114ebf /drivers/gpu/drm/i915/intel_crt.c
parentdrm/i915: Refactor platform specifics out of intel_get_shared_dpll() (diff)
downloadlinux-dev-daedf20a4f69685a636c9104cf6f1f5d8835345b.tar.xz
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drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.c
Move the code for selecting and configuring HSW/BDW DDI PLLs into the shared dpll infrastructure. With this most of the PLL selection logic for those platforms is in one place. DisplayPort is handled separately, but that should be fixed on a follow up patch. It also allows a small clean up of the SPLL logic. v2: Rebase. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-10-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5f12a195d55c..a2a31fd01d1d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -265,15 +265,9 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 24;
/* FDI must always be 2.7 GHz */
- if (HAS_DDI(dev)) {
- pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
+ if (HAS_DDI(dev))
pipe_config->port_clock = 135000 * 2;
- pipe_config->dpll_hw_state.wrpll = 0;
- pipe_config->dpll_hw_state.spll =
- SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
- }
-
return true;
}