diff options
| author |   Arkadiusz Hiler <arkadiusz.hiler@intel.com> | 2018-05-21 17:25:46 -0700 |
|---|---|---|
| committer |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-01 16:15:35 -0700 |
| commit | 5428bf5a9a9f28fae1ba2c57ba4ea8f8d358d10c (patch) | |
| tree | 35bbb3be39422f290bbef618ecc942d0340bc3b9 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | drm/i915/icl: Get DDI clock for ICL based on PLLs. (diff) | |
| download | linux-dev-5428bf5a9a9f28fae1ba2c57ba4ea8f8d358d10c.tar.xz linux-dev-5428bf5a9a9f28fae1ba2c57ba4ea8f8d358d10c.zip | |
drm/i915/icl: Calculate link clock using the new registers
Start using the new registers for ICL and on.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 3f042c505430..b344e0fe08fd 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1345,8 +1345,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, uint32_t cfgcr0, cfgcr1; uint32_t p0, p1, p2, dco_freq, ref_clock; - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); + if (INTEL_GEN(dev_priv) >= 11) { + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); + } else { + cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); + cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); + } p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK; |