diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-06-10 16:36:09 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-06-12 14:49:36 +0300 |
| commit | 4a95e36f0357ab4de6aeadfbe78ffe6af75b2fee (patch) | |
| tree | af92added1dbef1fd3d76e00b9aa78a553609575 /drivers/gpu/drm/i915/intel_display.c | |
| parent | drm/i915: Do not touch the PCH SSC reference if a PLL is using it (diff) | |
| download | linux-dev-4a95e36f0357ab4de6aeadfbe78ffe6af75b2fee.tar.xz linux-dev-4a95e36f0357ab4de6aeadfbe78ffe6af75b2fee.zip | |
drm/i915: Rename HSW/BDW PLL bits
Give the PLL control register bits better names on HSW/BDW.
v2: Fix the copy paste fails in SPLL_REF defines (Maarten)
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190610133609.27288-1-ville.syrjala@linux.intel.com
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 352c42826cb1..1b1ddb48ca7a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9134,12 +9134,12 @@ static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) if ((ctl & SPLL_PLL_ENABLE) == 0) return false; - if ((ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_SSC && + if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC && (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) return true; if (IS_BROADWELL(dev_priv) && - (ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_NON_SSC) + (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW) return true; return false; @@ -9154,11 +9154,11 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, if ((ctl & WRPLL_PLL_ENABLE) == 0) return false; - if ((ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_SSC) + if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC) return true; if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) && - (ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_NON_SSC && + (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW && (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) return true; |