diff options
| author |   Eric Anholt <eric@anholt.net> | 2010-01-28 16:45:52 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-02-26 13:23:20 -0800 |
| commit | c619eed4b2ee1b2bde3e02464eb81632a08bb976 (patch) | |
| tree | b017349c3626233d872b185efb38135f91b1abd5 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | drm/i915: Correct the Sandybridge chipset info structs. (diff) | |
| download | linux-dev-c619eed4b2ee1b2bde3e02464eb81632a08bb976.tar.xz linux-dev-c619eed4b2ee1b2bde3e02464eb81632a08bb976.zip | |
drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.
I think this is pretty much correct. Not really tested.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 439506cefc14..3ef3a0d0edd0 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -231,7 +231,7 @@ intel_dp_aux_ch(struct intel_output *intel_output, */ if (IS_eDP(intel_output)) aux_clock_divider = 225; /* eDP input clock at 450Mhz */ - else if (IS_IRONLAKE(dev)) + else if (HAS_PCH_SPLIT(dev)) aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ else aux_clock_divider = intel_hrawclk(dev) / 2; @@ -584,7 +584,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(3, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { if (intel_crtc->pipe == 0) { I915_WRITE(TRANSA_DATA_M1, ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | @@ -1176,7 +1176,7 @@ intel_dp_detect(struct drm_connector *connector) dp_priv->has_audio = false; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return ironlake_dp_detect(connector); temp = I915_READ(PORT_HOTPLUG_EN); |