diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-03-26 16:25:56 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-11 21:22:40 +0300 |
| commit | 4e2056e05e6eb646d37e310c11f6ac97a266b355 (patch) | |
| tree | bf9fbb82fa769b74b173611ecbd7106e1ce96f27 /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | drm/i915/icl: Switch to using 12 deep CSB status FIFO (diff) | |
| download | linux-dev-4e2056e05e6eb646d37e310c11f6ac97a266b355.tar.xz linux-dev-4e2056e05e6eb646d37e310c11f6ac97a266b355.zip | |
drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats
6bpc is only legal for RGB and RAW pixel encodings. For the rest
the minimum is 8bpc. Set our lower limit accordingly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190326142556.21176-6-ville.syrjala@linux.intel.com
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp_mst.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 9c4c0589c0fc..8839eaea8371 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -124,7 +124,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, limits.min_lane_count = limits.max_lane_count = intel_dp_max_lane_count(intel_dp); - limits.min_bpp = 6 * 3; + limits.min_bpp = intel_dp_min_bpp(pipe_config); limits.max_bpp = pipe_config->pipe_bpp; intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |