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| author |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-07-24 17:28:12 -0700 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-07-25 13:41:42 -0700 |
| commit | 340a44bef2342b0ff7334017e9e821645fa8ae43 (patch) | |
| tree | d58ca1fd131a5e1b0389dbd834d76afe5a9d28ba /drivers/gpu/drm/i915/intel_drv.h | |
| parent | drm/i915/icl: Update FIA supported lane count for hpd. (diff) | |
| download | linux-dev-340a44bef2342b0ff7334017e9e821645fa8ae43.tar.xz linux-dev-340a44bef2342b0ff7334017e9e821645fa8ae43.zip | |
drm/i915/icl: program MG_DP_MODE
Programming this register is part of the Enable Sequence for
DisplayPort on ICL. Do as the spec says.
v2: Simple rebase.
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725002813.6938-5-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5e225d8ba09a..4e5b00052b5b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1714,6 +1714,7 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits); void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits); +void icl_program_mg_dp_mode(struct intel_dp *intel_dp); void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |