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author | Satheeshakrishna M <satheeshakrishna.m@intel.com> | 2014-08-22 09:49:09 +0530 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-04-16 11:29:06 +0200 |
commit | dfb82408471ee2e56b26c05dcd50317f873bee57 (patch) | |
tree | d0c53fb958d47bddb3bd0222edba620a2dc51c66 /drivers/gpu/drm/i915/intel_drv.h | |
parent | drm/i915/bxt: fix panel fitter setup in crtc disable/enable (diff) | |
download | linux-dev-dfb82408471ee2e56b26c05dcd50317f873bee57.tar.xz linux-dev-dfb82408471ee2e56b26c05dcd50317f873bee57.zip |
drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence
Plug bxt PLL code into existing shared DPLL framework.
v2: (imre)
- squash in Satheeshakrishna's "Define BXT clock registers" and
"Add state variables for bxt clock registers" patches
- squash in Vandanas's "Change grp access to lane access for PLL"
- fix group vs. lane access in bxt_ddi_pll_get_hw_state
- add code comment why we read from lane registers while writing to
group registers
- clean up register macros
- use BXT_PORT_PLL_* macros instead of open-coding the same
- check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23
during hardware state readout
- add missing LANESTAGGER_STRAP_OVRD masking
- add note about missing step according to the latest BUN for
PORT_PLL_9/lockthresh
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
0 files changed, 0 insertions, 0 deletions