diff options
| author |   Hans de Goede <hdegoede@redhat.com> | 2017-03-01 15:15:01 +0200 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2017-03-01 15:57:57 +0200 |
| commit | 3e40fa8a3168da060e3835a17cf1ada5a837ddd6 (patch) | |
| tree | 3aa84f7f9f3af2fde93876ff4a9df999931e4812 /drivers/gpu/drm/i915/intel_dsi.c | |
| parent | drm/i915/dsi: Group DPOunit clock gate workaround with PLL enable (diff) | |
| download | linux-dev-3e40fa8a3168da060e3835a17cf1ada5a837ddd6.tar.xz linux-dev-3e40fa8a3168da060e3835a17cf1ada5a837ddd6.zip | |
drm/i915/dsi: Execute MIPI_SEQ_DEASSERT_RESET before calling device_ready()
Execute MIPI_SEQ_DEASSERT_RESET before putting the device in ready
state (LP-11), this is the sequence in which things should be done
according to the spec.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1488374106-4949-6-git-send-email-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index da798a579e11..b7b590d78b31 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -808,10 +808,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); msleep(intel_dsi->panel_on_delay); - /* put device in ready state */ + /* Deassert reset */ + intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); + + /* Put device in ready state (LP-11) */ intel_dsi_device_ready(encoder); - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); + /* Send initialization commands in LP mode */ intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); /* Enable port in pre-enable phase itself because as per hw team @@ -915,6 +918,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); + /* Transition to LP-00 */ intel_dsi_clear_device_ready(encoder); if (IS_BROXTON(dev_priv)) { @@ -938,6 +942,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, I915_WRITE(DSPCLK_GATE_D, val); } + /* Assert reset */ intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); /* Power off, try both CRC pmic gpio and VBT */ |