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| author |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2015-02-13 17:23:43 -0200 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-23 23:59:57 +0100 |
| commit | e489e38e3f880ec3ff3281c5ceafa3b750600556 (patch) | |
| tree | d8fec3b2a71b66314b6a6beff608eba8e27716ae /drivers/gpu/drm/i915/intel_fbc.c | |
| parent | drm/i915: HSW+ FBC is tied to pipe A (diff) | |
| download | linux-dev-e489e38e3f880ec3ff3281c5ceafa3b750600556.tar.xz linux-dev-e489e38e3f880ec3ff3281c5ceafa3b750600556.zip | |
drm/i915: gen5+ can have FBC with multiple pipes
So allow it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_fbc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 6406b1432a2e..618f7bdab0ba 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -477,17 +477,19 @@ static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) { struct drm_crtc *crtc = NULL, *tmp_crtc; enum pipe pipe; - bool pipe_a_only = false; + bool pipe_a_only = false, one_pipe_only = false; if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) pipe_a_only = true; + else if (INTEL_INFO(dev_priv)->gen <= 4) + one_pipe_only = true; for_each_pipe(dev_priv, pipe) { tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; if (intel_crtc_active(tmp_crtc) && to_intel_crtc(tmp_crtc)->primary_enabled) { - if (crtc) { + if (one_pipe_only && crtc) { if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); return NULL; |