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| author |   Alex Dai <yu.dai@intel.com> | 2015-09-25 11:46:56 -0700 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-30 17:15:12 +0200 |
| commit | 93f253187c2f565678bd7e5ca5f64c1043774f1b (patch) | |
| tree | 94f192d9534985030b65c03a96c781efbb5c243b /drivers/gpu/drm/i915/intel_guc_fwif.h | |
| parent | drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/ (diff) | |
| download | linux-dev-93f253187c2f565678bd7e5ca5f64c1043774f1b.tar.xz linux-dev-93f253187c2f565678bd7e5ca5f64c1043774f1b.zip | |
drm/i915/guc: Media domain bit needed when notify GuC rc6 state
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.
v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating
v1: Add parameters definition to avoid magic value
Signed-off-by: Alex Dai <yu.dai@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_fwif.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_fwif.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index e1f47ba2b4b0..6c78fdf685e2 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -218,6 +218,9 @@ struct guc_context_desc { u64 desc_private; } __packed; +#define GUC_FORCEWAKE_RENDER (1 << 0) +#define GUC_FORCEWAKE_MEDIA (1 << 1) + /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ enum host2guc_action { HOST2GUC_ACTION_DEFAULT = 0x0, |