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| author |   Michal Wajdeczko <michal.wajdeczko@intel.com> | 2019-05-27 18:36:06 +0000 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-05-28 10:07:13 +0100 |
| commit | 7c5ae251b048edc540a1dd245654fcc79f63a531 (patch) | |
| tree | 4b3b9947b348a02e21ee9834f270912abcc28446 /drivers/gpu/drm/i915/intel_guc_reg.h | |
| parent | drm/i915/guc: New GuC scratch registers for Gen11 (diff) | |
| download | linux-dev-7c5ae251b048edc540a1dd245654fcc79f63a531.tar.xz linux-dev-7c5ae251b048edc540a1dd245654fcc79f63a531.zip | |
drm/i915/huc: New HuC status register for Gen11
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
v2: use reg/mask/value instead of dedicated functions (Daniele)
BSpec: 19686
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-11-michal.wajdeczko@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index d26de5193568..7eba65795b58 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -79,6 +79,9 @@ #define HUC_STATUS2 _MMIO(0xD3B0) #define HUC_FW_VERIFIED (1<<7) +#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC) +#define HUC_LOAD_SUCCESSFUL (1 << 0) + #define GUC_WOPCM_SIZE _MMIO(0xc050) #define GUC_WOPCM_SIZE_LOCKED (1<<0) #define GUC_WOPCM_SIZE_SHIFT 12 |