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author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2021-07-21 15:30:29 -0700 |
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committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-22 09:25:42 -0700 |
commit | 22e26af769035c61430bc43b7e0639404a14cbe1 (patch) | |
tree | f189bd93764dbfc2a71b4791a1a424994e08d2db /drivers/gpu/drm/i915/intel_pch.c | |
parent | Merge branch 'topic/xehp-dg2-definitions-2021-07-21' into drm-intel-next (diff) | |
download | linux-dev-22e26af769035c61430bc43b7e0639404a14cbe1.tar.xz linux-dev-22e26af769035c61430bc43b7e0639404a14cbe1.zip |
drm/i915: Fork DG1 interrupt handler
The current interrupt handler is getting increasingly complicated and
Xe_HP changes will bring even more complexity. Let's split off a new
interrupt handler starting with DG1 (i.e., when the master tile
interrupt register was added to the design) and use that as the basis
for the new Xe_HP changes.
Now that we track the hardware IP's release number as well as the
version number, we can also properly define DG1 has version "12.10" and
replace the has_master_unit_irq feature flag with an IP version test.
Bspec: 50875
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-5-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pch.c')
0 files changed, 0 insertions, 0 deletions