diff options
| author |   Jani Nikula <jani.nikula@intel.com> | 2022-02-23 12:35:17 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-02-28 15:47:35 +0200 |
| commit | 5c190e5394cc7773feaff1b54701a2c2f73ef011 (patch) | |
| tree | 08371734e66c7a340b761bc1f6c2c3f1e30b7ca1 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Fix MSO vs. bigjoiner timings confusion (diff) | |
| download | linux-dev-5c190e5394cc7773feaff1b54701a2c2f73ef011.tar.xz linux-dev-5c190e5394cc7773feaff1b54701a2c2f73ef011.zip | |
drm/i915/wm: use REG_FIELD_{PREP,GET} for PLANE_WM_BLOCKS_MASK
Use REG_FIELD_{PREP,GET} for completeness, and to avoid bitwise
operations with different sizes.
v2: Also use REG_FIELD_GET in skl_wm_level_from_reg_val() (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220223103517.634229-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 51308211618e..b9d711246f1e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5931,7 +5931,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, val |= PLANE_WM_EN; if (level->ignore_lines) val |= PLANE_WM_IGNORE_LINES; - val |= level->blocks; + val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); intel_de_write_fw(dev_priv, reg, val); @@ -6579,7 +6579,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) { level->enable = val & PLANE_WM_EN; level->ignore_lines = val & PLANE_WM_IGNORE_LINES; - level->blocks = val & PLANE_WM_BLOCKS_MASK; + level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); } |