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| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2015-01-12 06:14:31 -0800 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-01-13 00:31:55 +0100 |
| commit | e85a5c7989c5be8fe30acc35eba9fb54b3450f36 (patch) | |
| tree | 56a5992c36ec575bcd6bab04e085084f37161703 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Improve HiZ throughput on Cherryview. (diff) | |
| download | linux-dev-e85a5c7989c5be8fe30acc35eba9fb54b3450f36.tar.xz linux-dev-e85a5c7989c5be8fe30acc35eba9fb54b3450f36.zip | |
Revert "drm/i915/chv: Use timeout mode for RC6 on chv"
This reverts commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7.
Although timeout mode allows higher residency it impact badly on performance.
I believe while we don't have a way to balance between performance and
power savings at runtime I believe we have to revert and prioritize
performance that was impacted a lot.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88103
Cc: Deepak S <deepak.s@linux.intel.com>
Cc: Wendy Wang <wendy.wang@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3ba446a69ecd..66a1c7f66973 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4689,8 +4689,7 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ - I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); + I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ /* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, @@ -4704,7 +4703,7 @@ static void cherryview_enable_rps(struct drm_device *dev) /* 3: Enable RC6 */ if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && (pcbr >> VLV_PCBR_ADDR_SHIFT)) - rc6_mode = GEN7_RC_CTL_TO_MODE; + rc6_mode = GEN6_RC_CTL_EI_MODE(1); I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |