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| author |   Ben Widawsky <benjamin.widawsky@intel.com> | 2013-10-04 21:22:54 -0700 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-10 12:47:09 +0200 |
| commit | 4032ef4315475dd9605d6cde461168fb85d776ea (patch) | |
| tree | afc655e39cee864255cb49657d4e30d1e0c549ac /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Create GEN specific read MMIO (diff) | |
| download | linux-dev-4032ef4315475dd9605d6cde461168fb85d776ea.tar.xz linux-dev-4032ef4315475dd9605d6cde461168fb85d776ea.zip | |
drm/i915: Create GEN specific write MMIO
Similar to the previous patch which implemented GEN specific reads; this
patch does the same for writes. Writes have a bit of adding complexity
due to the FPGA_DBG feature of HSW plus:
gen[2-4]: nothing special
gen5: ILK dummy write
gen[6-7]: forcewake shenanigans
gen[HSW}: forcewake shenanigans + FPGA_DBG
I was a bit torn about whether or not to combine 6-HSW as one function,
since the FPGA_DBG is cleanly separated, and it wouldn't make the 6-7
MMIO too messy. In the end, I chose the clearest possible solution which
splits out HSW.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions