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authorArun Siluvery <arun.siluvery@linux.intel.com>2014-10-28 18:33:14 +0000
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-14 10:29:15 +0100
commit952890098a14043fe7acc5f595c6306c69baf40d (patch)
tree2a05262fb0e966330c08c1a86b6598b17e611188 /drivers/gpu/drm/i915/intel_ringbuffer.c
parentdrm/i915/chv: Combine GEN8_ROW_CHICKEN w/a (diff)
downloadlinux-dev-952890098a14043fe7acc5f595c6306c69baf40d.tar.xz
linux-dev-952890098a14043fe7acc5f595c6306c69baf40d.zip
drm/i915/chv: Add new workarounds for chv
+WaForceEnableNonCoherent:chv +WaHdcDisableFetchWhenMasked:chv For: VIZ-4090 Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1df79a952291..a09aae70e579 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -793,6 +793,16 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
STALL_DOP_GATING_DISABLE);
+ /* Use Force Non-Coherent whenever executing a 3D context. This is a
+ * workaround for a possible hang in the unlikely event a TLB
+ * invalidation occurs during a PSD flush.
+ */
+ /* WaForceEnableNonCoherent:chv */
+ /* WaHdcDisableFetchWhenMasked:chv */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT |
+ HDC_DONOT_FETCH_MEM_WHEN_MASKED);
+
return 0;
}