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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2010-12-22 14:04:47 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-11 20:35:41 +0000 |
| commit | 55249baaa5cd188ebd9acdb047eeaed8092e4a93 (patch) | |
| tree | ec52e1bdb516ce0bd259614b3c068960450b9236 /drivers/gpu/drm/i915/intel_ringbuffer.h | |
| parent | drm/i915: Use the mappable sizes determined by GTT for consistency. (diff) | |
| download | linux-dev-55249baaa5cd188ebd9acdb047eeaed8092e4a93.tar.xz linux-dev-55249baaa5cd188ebd9acdb047eeaed8092e4a93.zip | |
drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines
On i830 if the tail pointer is set to within 2 cachelines of the end of
the buffer, the chip may hang. So instead if the tail were to land in
that location, we pad the end of the buffer with NOPs, and start again
at the beginning.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8e2e357ad6ee..bbbf505c8b56 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -49,6 +49,7 @@ struct intel_ring_buffer { u32 tail; int space; int size; + int effective_size; struct intel_hw_status_page status_page; u32 irq_seqno; /* last seq seem at irq time */ |