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| author |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-22 17:56:33 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-06-05 08:52:29 +0200 |
| commit | 85ab3998c6ea28e2794a63b58cf52b634de1ddac (patch) | |
| tree | a1a2e28c212901ec1c2ccfc00b264844c48dd8f3 /drivers/gpu/drm/i915/intel_uncore.c | |
| parent | drm/i915: Fix up fifo underrun tracking, take N (diff) | |
| download | linux-dev-85ab3998c6ea28e2794a63b58cf52b634de1ddac.tar.xz linux-dev-85ab3998c6ea28e2794a63b58cf52b634de1ddac.zip | |
drm/i915: Disable gpu reset on i965g/gm
Ville figured out that it needs a full display reset since apparently
a lot more goes down than just the GT. Until that's address it's
better to just diable gpu reset.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9cd99d9676fd..1dbabb071c08 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -965,6 +965,9 @@ static int i965_do_reset(struct drm_device *dev) { int ret; + /* FIXME: i965g/gm need a display save/restore for gpu reset. */ + return -ENODEV; + /* * Set the domains we want to reset (GRDOM/bits 2 and 3) as * well as the reset bit (GR/bit 0). Setting the GR bit |