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authorJani Nikula <jani.nikula@intel.com>2020-11-30 13:16:01 +0200
committerJani Nikula <jani.nikula@intel.com>2020-12-02 17:29:46 +0200
commit54b3f0e6817314ff6b9a354c32a4ff217cea33d1 (patch)
treeacf8638485ca333299273e124e0df49d1c6e51c6 /drivers/gpu/drm/i915/intel_uncore.h
parentRevert "drm/i915/display/fbc: Disable fbc by default on TGL" (diff)
downloadlinux-dev-54b3f0e6817314ff6b9a354c32a4ff217cea33d1.tar.xz
linux-dev-54b3f0e6817314ff6b9a354c32a4ff217cea33d1.zip
drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()
Good riddance! Remove the macros and their remaining references in comments. The following functions should be used instead, depending on the use case: - intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read() - intel_de_read(), intel_de_write(), intel_de_posting_read() Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201130111601.2817-10-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.h')
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 5dcb7f4183b2..59f0da8f1fbb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -318,8 +318,8 @@ __uncore_write(write_notrace, 32, l, false)
* will be implemented using 2 32-bit writes in an arbitrary order with
* an arbitrary delay between them. This can cause the hardware to
* act upon the intermediate value, possibly leading to corruption and
- * machine death. For this reason we do not support I915_WRITE64, or
- * uncore->funcs.mmio_writeq.
+ * machine death. For this reason we do not support intel_uncore_write64,
+ * or uncore->funcs.mmio_writeq.
*
* When reading a 64-bit value as two 32-bit values, the delay may cause
* the two reads to mismatch, e.g. a timestamp overflowing. Also note that