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| author |   Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-03-25 14:49:38 -0700 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-03-26 20:16:45 +0000 |
| commit | d2d551c06f81775baae3afb69fae3252271190f9 (patch) | |
| tree | d3af73e4bcb45df1269d81055620beedb7def7bd /drivers/gpu/drm/i915/intel_uncore.h | |
| parent | drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore (diff) | |
| download | linux-dev-d2d551c06f81775baae3afb69fae3252271190f9.tar.xz linux-dev-d2d551c06f81775baae3afb69fae3252271190f9.zip | |
drm/i915: intel_wait_for_register_fw to uncore
The intel_uncore structure is the owner of register access, so
subclass the function to it.
While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-8-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.h | 34 |
1 files changed, 21 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index e3c2c37c51e2..7d83fbd8fc2d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -220,31 +220,32 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value); -static inline -int intel_wait_for_register(struct drm_i915_private *dev_priv, - i915_reg_t reg, - u32 mask, - u32 value, - unsigned int timeout_ms) +static inline int +intel_wait_for_register(struct drm_i915_private *dev_priv, + i915_reg_t reg, + u32 mask, + u32 value, + unsigned int timeout_ms) { return __intel_wait_for_register(dev_priv, reg, mask, value, 2, timeout_ms, NULL); } -int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv, + +int __intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value); -static inline -int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, - i915_reg_t reg, - u32 mask, - u32 value, +static inline int +intel_wait_for_register_fw(struct intel_uncore *uncore, + i915_reg_t reg, + u32 mask, + u32 value, unsigned int timeout_ms) { - return __intel_wait_for_register_fw(dev_priv, reg, mask, value, + return __intel_wait_for_register_fw(uncore, reg, mask, value, 2, timeout_ms, NULL); } @@ -367,6 +368,13 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore, #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__) #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__)) +static inline void intel_uncore_rmw_or_fw(struct intel_uncore *uncore, + i915_reg_t reg, u32 or_val) +{ + intel_uncore_write_fw(uncore, reg, + intel_uncore_read_fw(uncore, reg) | or_val); +} + #define raw_reg_read(base, reg) \ readl(base + i915_mmio_reg_offset(reg)) #define raw_reg_write(base, reg, value) \ |