diff options
| author |   Damien Lespiau <damien.lespiau@intel.com> | 2014-03-26 18:41:51 +0000 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-28 18:33:13 +0100 |
| commit | 5d708680eac2a8e2a0981007278a759df738d15b (patch) | |
| tree | 9436cada8da7fe91a805fd7d6bd6b4b0864ffa57 /drivers/gpu/drm/i915 | |
| parent | drm/i915: Undo gtt scratch pte unmapping again (diff) | |
| download | linux-dev-5d708680eac2a8e2a0981007278a759df738d15b.tar.xz linux-dev-5d708680eac2a8e2a0981007278a759df738d15b.zip | |
drm/i915/bdw: Implement Wa4x4STCOptimizationDisable:bdw
Not implementing this W/A can lead to hangs.
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rafael Barbalho <rafael.barbalho@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 74f7d853eb58..d90dc20077e3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -973,7 +973,8 @@ enum punit_power_well { #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) #define GEN6_BLITTER_ECOSKPD 0x221d0 #define GEN6_BLITTER_LOCK_SHIFT 16 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c1e2d75f4c40..b66a43b90d1b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4882,6 +4882,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) /* WaDisableSDEUnitClockGating:bdw */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + + /* Wa4x4STCOptimizationDisable:bdw */ + I915_WRITE(CACHE_MODE_1, + _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); } static void haswell_init_clock_gating(struct drm_device *dev) |