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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-05 18:08:37 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-07 21:35:45 +0200 |
| commit | 5f4f3e386b36952b2fa3d3935342a25d6e1c6d28 (patch) | |
| tree | 77e92555e8d29e915e7278c47bb265dc570a9c05 /drivers/gpu/drm/i915 | |
| parent | drm/i915: Split the gamma/csc enable bits from the plane_ctl() function (diff) | |
| download | linux-dev-5f4f3e386b36952b2fa3d3935342a25d6e1c6d28.tar.xz linux-dev-5f4f3e386b36952b2fa3d3935342a25d6e1c6d28.zip | |
drm/i915: Precompute gamma_mode
We shouldn't be computing gamma mode during the commit phase.
Move it to the check phase.
v2: Reword comments a bit (Matt)
Rebase
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190205160848.24662-3-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 31fa599b0d61..057f0600840a 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state) reenable_ips = true; } - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; - I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT); + I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); i9xx_load_luts(crtc_state); @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, INTEL_INFO(dev_priv)->color.degamma_lut_size); - crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); - POSTING_READ(GAMMA_MODE(pipe)); + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode); /* * Reset the index, otherwise it prevents the legacy palette to be @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, 0); - crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT; - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT); - POSTING_READ(GAMMA_MODE(pipe)); + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode); } /* Loads the palette/gamma unit for the CRTC on CherryView. */ @@ -634,8 +629,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state) gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; /* Always allow legacy gamma LUT with no further checking. */ - if (crtc_state_is_legacy_gamma(crtc_state)) + if (crtc_state_is_legacy_gamma(crtc_state)) { + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; return 0; + } if (check_lut_size(crtc_state->base.degamma_lut, degamma_length) || check_lut_size(crtc_state->base.gamma_lut, gamma_length)) @@ -645,6 +642,12 @@ int intel_color_check(struct intel_crtc_state *crtc_state) drm_color_lut_check(crtc_state->base.gamma_lut, gamma_tests)) return -EINVAL; + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT; + else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; + else + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; return 0; } |