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| author |   Imre Deak <imre.deak@intel.com> | 2021-09-06 21:27:13 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-09-23 16:13:27 +0300 |
| commit | 929dd111dcf8395e72635e0e7a4e502a6bb6b3d0 (patch) | |
| tree | ef4fb2662e0fa1e90f06b39e2c9b0c65f5dcebe6 /drivers/gpu/drm/i915 | |
| parent | drm/i915/adlp: Assert that VMAs in DPT start at 0 (diff) | |
| download | linux-dev-929dd111dcf8395e72635e0e7a4e502a6bb6b3d0.tar.xz linux-dev-929dd111dcf8395e72635e0e7a4e502a6bb6b3d0.zip | |
drm/i915: Follow a new->old platform check order in intel_fb_stride_alignment
Follow the usual new->old order in intel_fb_stride_alignment() platform
check ladder.
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-5-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fb.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a0db67e85c71..479c76c7958c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1159,6 +1159,12 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) tile_width = intel_tile_width_bytes(fb, color_plane); if (is_ccs_modifier(fb->modifier)) { /* + * On TGL the surface stride must be 4 tile aligned, mapped by + * one 64 byte cacheline on the CCS AUX surface. + */ + if (DISPLAY_VER(dev_priv) >= 12) + tile_width *= 4; + /* * Display WA #0531: skl,bxt,kbl,glk * * Render decompression and plane width > 3840 @@ -1167,14 +1173,8 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && - color_plane == 0 && fb->width > 3840) - tile_width *= 4; - /* - * The main surface pitch must be padded to a multiple of four - * tile widths. - */ - else if (DISPLAY_VER(dev_priv) >= 12) + else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && + color_plane == 0 && fb->width > 3840) tile_width *= 4; } return tile_width; |