diff options
| author |   Jordan Crouse <jcrouse@codeaurora.org> | 2020-09-03 20:03:13 -0600 |
|---|---|---|
| committer |   Rob Clark <robdclark@chromium.org> | 2020-09-04 12:14:15 -0700 |
| commit | f6828e0c4045f03f9cf2df6c2a768102641183f4 (patch) | |
| tree | c07c6625cf359e2e95aca5b864b9e159a27eea99 /drivers/gpu/drm/msm/adreno/a4xx_gpu.c | |
| parent | drm/msm: Disable preemption on all 5xx targets (diff) | |
| download | linux-dev-f6828e0c4045f03f9cf2df6c2a768102641183f4.tar.xz linux-dev-f6828e0c4045f03f9cf2df6c2a768102641183f4.zip | |
drm/msm: Disable the RPTR shadow
Disable the RPTR shadow across all targets. It will be selectively
re-enabled later for targets that need it.
Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a4xx_gpu.c')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index b9b26b2bf9c5..954753600625 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -267,6 +267,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu) if (ret) return ret; + /* + * Use the default ringbuffer size and block size but disable the RPTR + * shadow + */ + gpu_write(gpu, REG_A4XX_CP_RB_CNTL, + MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); + + /* Set the ringbuffer address */ + gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); + /* Load PM4: */ ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4; |