diff options
| author |   Drew Davenport <ddavenport@chromium.org> | 2019-12-06 16:13:43 -0700 |
|---|---|---|
| committer |   Rob Clark <robdclark@chromium.org> | 2020-01-02 16:09:15 -0800 |
| commit | 99beed68c3c72e74c064bb30fb6fd9346f454f50 (patch) | |
| tree | dfa0df51709ef9f4a7e265430d23073782b9b08d /drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | |
| parent | drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state (diff) | |
| download | linux-dev-99beed68c3c72e74c064bb30fb6fd9346f454f50.tar.xz linux-dev-99beed68c3c72e74c064bb30fb6fd9346f454f50.zip | |
drm/msm/dpu: Remove unnecessary NULL checks
dpu_hw_ctl* is checked for NULL when passed as an argument
to several functions. It will never be NULL, so remove the
checks.
Signed-off-by: Drew Davenport <ddavenport@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 047960949fbb..cfd01b0ac7f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -62,7 +62,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( return; ctl = phys_enc->hw_ctl; - if (!ctl || !ctl->ops.setup_intf_cfg) + if (!ctl->ops.setup_intf_cfg) return; intf_cfg.intf = phys_enc->intf_idx; @@ -125,7 +125,7 @@ static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; - if (!phys_enc || !phys_enc->hw_ctl) + if (!phys_enc) return; DPU_ATRACE_BEGIN("ctl_start_irq"); @@ -198,7 +198,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; bool do_log = false; - if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl) + if (!phys_enc || !phys_enc->hw_pp) return -EINVAL; cmd_enc->pp_timeout_report_cnt++; @@ -428,7 +428,7 @@ static void _dpu_encoder_phys_cmd_pingpong_config( struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp + if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0); return; @@ -458,7 +458,7 @@ static void dpu_encoder_phys_cmd_enable_helper( struct dpu_hw_ctl *ctl; u32 flush_mask = 0; - if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) { + if (!phys_enc || !phys_enc->hw_pp) { DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); return; } @@ -614,7 +614,7 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_wait_info wait_info; int ret; - if (!phys_enc || !phys_enc->hw_ctl) { + if (!phys_enc) { DPU_ERROR("invalid argument(s)\n"); return -EINVAL; } |