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| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-05-16 23:29:08 +0300 |
|---|---|---|
| committer |   Rob Clark <robdclark@chromium.org> | 2021-06-23 07:32:15 -0700 |
| commit | 597762d5bf5024e7c7a079a66d056d983e1a40f2 (patch) | |
| tree | 8b2b4356dc02526bf7274db213d66b759831992c /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | |
| parent | drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock (diff) | |
| download | linux-dev-597762d5bf5024e7c7a079a66d056d983e1a40f2.tar.xz linux-dev-597762d5bf5024e7c7a079a66d056d983e1a40f2.zip | |
drm/msm/dpu: define interrupt register names
In order to make mdss_irqs readable (and error-prone) define names for
interrupt register indices.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210516202910.2141079-4-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 5bade5637ecc..b26a3445a8eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -74,6 +74,24 @@ enum dpu_intr_type { DPU_IRQ_TYPE_RESERVED, }; +/* When making changes be sure to sync with dpu_intr_set */ +enum dpu_hw_intr_reg { + MDP_SSPP_TOP0_INTR, + MDP_SSPP_TOP0_INTR2, + MDP_SSPP_TOP0_HIST_INTR, + MDP_INTF0_INTR, + MDP_INTF1_INTR, + MDP_INTF2_INTR, + MDP_INTF3_INTR, + MDP_INTF4_INTR, + MDP_AD4_0_INTR, + MDP_AD4_1_INTR, + MDP_INTF0_7xxx_INTR, + MDP_INTF1_7xxx_INTR, + MDP_INTF5_7xxx_INTR, + MDP_INTR_MAX, +}; + struct dpu_hw_intr; /** |