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| author |   Jeykumar Sankaran <jsanka@codeaurora.org> | 2018-09-05 19:08:10 -0700 |
|---|---|---|
| committer |   Rob Clark <robdclark@gmail.com> | 2018-10-03 20:24:50 -0400 |
| commit | ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8 (patch) | |
| tree | 140dd03d7d61a181340ffdfcaedeaa139135f895 /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | |
| parent | drm/msm/dpu: Remove dpu_mdss_isr when dpu_mdss_destroy is called (diff) | |
| download | linux-dev-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.tar.xz linux-dev-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.zip | |
drm/msm/dpu: remove debugfs support for misr
MISR support is the debug feature present in Snapdragon chipsets.
At the layer mixer and interfaces, MISR algorithm can generate CRC
signatures of the pixel data which can be used for validating
the frames generated. Since there are no clients for this feature,
strip down the support from the driver.
changes in v4:
- changed introduced in the series
changes in v5:
- update commit text with the need for the change(Sean)
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 4ab72b0f07a5..acb8dc8acaa5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -34,9 +34,6 @@ #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 -#define LM_MISR_CTRL 0x310 -#define LM_MISR_SIGNATURE 0x314 - static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, struct dpu_mdss_cfg *m, void __iomem *addr, @@ -171,30 +168,6 @@ static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer, { } -static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, - bool enable, u32 frame_count) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 config = 0; - - DPU_REG_WRITE(c, LM_MISR_CTRL, MISR_CTRL_STATUS_CLEAR); - /* clear misr data */ - wmb(); - - if (enable) - config = (frame_count & MISR_FRAME_COUNT_MASK) | - MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK; - - DPU_REG_WRITE(c, LM_MISR_CTRL, config); -} - -static u32 dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - - return DPU_REG_READ(c, LM_MISR_SIGNATURE); -} - static void _setup_mixer_ops(struct dpu_mdss_cfg *m, struct dpu_hw_lm_ops *ops, unsigned long features) @@ -207,8 +180,6 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m, ops->setup_alpha_out = dpu_hw_lm_setup_color3; ops->setup_border_color = dpu_hw_lm_setup_border_color; ops->setup_gc = dpu_hw_lm_gc; - ops->setup_misr = dpu_hw_lm_setup_misr; - ops->collect_misr = dpu_hw_lm_collect_misr; }; static struct dpu_hw_blk_ops dpu_hw_ops = { |