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| author |   Kalyan Thota <kalyan_t@codeaurora.org> | 2020-11-25 02:02:40 -0800 |
|---|---|---|
| committer |   Rob Clark <robdclark@chromium.org> | 2020-11-29 11:08:20 -0800 |
| commit | 0c3d3cc93811c9b2413a17e06a91ca39a19ad871 (patch) | |
| tree | 1cf944e8c3f5e223677423fa574080d7f98376b9 /drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | |
| parent | drm/msm/a6xx: Add support for using system cache on MMU500 based targets (diff) | |
| download | linux-dev-0c3d3cc93811c9b2413a17e06a91ca39a19ad871.tar.xz linux-dev-0c3d3cc93811c9b2413a17e06a91ca39a19ad871.zip | |
drm/msm/dpu: consider vertical front porch in the prefill bw calculation
In case of panels with low vertical back porch, the prefill bw
requirement will be high as we will have less time(vbp+pw) to
fetch and fill the hw latency buffers before start of first line
in active period.
For ex:
Say hw_latency_line_buffers = 24, and if blanking vbp+pw = 10
Here we need to fetch 24 lines of data in 10 line times.
This will increase the bw to the ratio of linebuffers to blanking.
DPU hw can also fetch data during vertical front porch provided
interface prefetch is enabled. Use vfp in the prefill calculation
as dpu driver enables prefetch if the blanking is not sufficient
to fill the latency lines.
Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index cf0084d7cc7c..f679979ae045 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -161,7 +161,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, u64 plane_bw; u32 hw_latency_lines; u64 scale_factor; - int vbp, vpw; + int vbp, vpw, vfp; pstate = to_dpu_plane_state(plane->state); mode = &plane->state->crtc->mode; @@ -174,6 +174,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, fps = drm_mode_vrefresh(mode); vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; + vfp = mode->vsync_start - mode->vdisplay; hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -186,7 +187,13 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, src_width * hw_latency_lines * fps * fmt->bpp * scale_factor * mode->vtotal; - do_div(plane_prefill_bw, (vbp+vpw)); + if ((vbp+vpw) > hw_latency_lines) + do_div(plane_prefill_bw, (vbp+vpw)); + else if ((vbp+vpw+vfp) < hw_latency_lines) + do_div(plane_prefill_bw, (vbp+vpw+vfp)); + else + do_div(plane_prefill_bw, hw_latency_lines); + pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); } |