diff options
author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-03-31 13:57:21 +0300 |
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committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 11:05:45 -0700 |
commit | 5d13459650b3668edcd6d180787aac38d001c4ed (patch) | |
tree | 5d1988a6c26c4e04ec230ddf27275260a55a6e2a /drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | |
parent | drm/msm/dsi: remove msm_dsi_pll_set_usecase (diff) | |
download | linux-dev-5d13459650b3668edcd6d180787aac38d001c4ed.tar.xz linux-dev-5d13459650b3668edcd6d180787aac38d001c4ed.zip |
drm/msm/dsi: push provided clocks handling into a generic code
All MSM DSI PHYs provide two clocks: byte and pixel ones.
Register/unregister provided clocks from the generic place, removing
boilerplate code from all MSM DSI PHY drivers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-11-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c')
-rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 63 |
1 files changed, 8 insertions, 55 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index d267b25e5da0..3446be318648 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -31,15 +31,10 @@ #define POLL_MAX_READS 10 #define POLL_TIMEOUT_US 50 -#define NUM_PROVIDED_CLKS 2 - #define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000 -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 - /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) @@ -83,10 +78,6 @@ struct dsi_pll_28nm { struct clk *clks[NUM_DSI_CLOCKS_MAX]; u32 num_clks; - /* clock-provider: */ - struct clk *provided_clks[NUM_PROVIDED_CLKS]; - struct clk_onecell_data clk_data; - struct pll_28nm_cached_state cached_state; }; @@ -495,38 +486,16 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) return 0; } -static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, - struct clk **byte_clk_provider, - struct clk **pixel_clk_provider) -{ - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - if (byte_clk_provider) - *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; - if (pixel_clk_provider) - *pixel_clk_provider = - pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; - - return 0; -} - static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - int i; - - msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, - pll_28nm->clks, pll_28nm->num_clks); - for (i = 0; i < NUM_PROVIDED_CLKS; i++) - pll_28nm->provided_clks[i] = NULL; + msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks); pll_28nm->num_clks = 0; - pll_28nm->clk_data.clks = NULL; - pll_28nm->clk_data.clk_num = 0; } -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { @@ -538,9 +507,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) }; struct device *dev = &pll_28nm->pdev->dev; struct clk **clks = pll_28nm->clks; - struct clk **provided_clks = pll_28nm->provided_clks; int num = 0; - int ret; DBG("%d", pll_28nm->id); @@ -564,11 +531,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); - clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = - clk_register_divider(dev, clk_name, + clks[num++] = clk_register_divider(dev, clk_name, parent1, 0, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, 0, 8, 0, NULL); + provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]); snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); @@ -581,22 +548,12 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); - clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = - clk_register_fixed_factor(dev, clk_name, + clks[num++] = clk_register_fixed_factor(dev, clk_name, parent1, CLK_SET_RATE_PARENT, 1, 4); + provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]); pll_28nm->num_clks = num; - pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; - pll_28nm->clk_data.clks = provided_clks; - - ret = of_clk_add_provider(dev->of_node, - of_clk_src_onecell_get, &pll_28nm->clk_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret); - return ret; - } - return 0; } @@ -625,14 +582,13 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; + pll->cfg = phy->cfg; if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) pll_28nm->vco_delay = 1000; else pll_28nm->vco_delay = 1; - pll->cfg = phy->cfg; - - ret = pll_28nm_register(pll_28nm); + ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); return ret; @@ -802,7 +758,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, @@ -830,7 +785,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, @@ -858,7 +812,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .pll_init = dsi_pll_28nm_init, }, .pll_ops = { - .get_provider = dsi_pll_28nm_get_provider, .destroy = dsi_pll_28nm_destroy, .save_state = dsi_pll_28nm_save_state, .restore_state = dsi_pll_28nm_restore_state, |