diff options
| author |   Stephen Boyd <sboyd@kernel.org> | 2019-08-30 08:09:21 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-01-06 23:10:05 -0800 |
| commit | 9611b3aacc1c1af7cb96d35ca5f1e55fdd44f697 (patch) | |
| tree | 53ace3d3ed2421ad7607bc69c1c66f1ade6e78ee /drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | |
| parent | clk: asm9260: Use parent accuracy in fixed rate clk (diff) | |
| download | linux-dev-9611b3aacc1c1af7cb96d35ca5f1e55fdd44f697.tar.xz linux-dev-9611b3aacc1c1af7cb96d35ca5f1e55fdd44f697.zip | |
clk: mux: Add support for specifying parents via DT/pointers
After commit fc0c209c147f ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a mux clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.
Note: the msm drm driver passes an anonymous array through the macro
which seems to confuse my compiler. Adding a parenthesis around the
whole thing at the call site seems to fix it but it must be wrong. Maybe
it's better to split this patch and pick out the array bits there?
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-11-sboyd@kernel.org
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 8f6100db90ed..1c894548dd72 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -751,9 +751,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); hw = clk_hw_register_mux(dev, clk_name, - (const char *[]){ + ((const char *[]){ parent, parent2, parent3, parent4 - }, 4, 0, pll_10nm->phy_cmn_mmio + + }), 4, 0, pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); if (IS_ERR(hw)) { |