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| author |   Ben Skeggs <bskeggs@redhat.com> | 2014-01-09 13:03:17 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-23 13:38:45 +1000 |
| commit | cb1567c2861432e83210f01ddb0560c4ae64f9ed (patch) | |
| tree | f1a2902171a243a7dd385c52c3f6bdec054f1167 /drivers/gpu/drm/nouveau/core/engine/fifo | |
| parent | drm/nve0/fifo: keep mmu fault interrupts enabled at all times (diff) | |
| download | linux-dev-cb1567c2861432e83210f01ddb0560c4ae64f9ed.tar.xz linux-dev-cb1567c2861432e83210f01ddb0560c4ae64f9ed.zip | |
drm/nve0/fifo: recover from mmu faults on bar1/bar3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/fifo')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 31 |
1 files changed, 20 insertions, 11 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 3bf5ba8804e9..1eb06b29a9db 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -384,8 +384,8 @@ static const struct nouveau_enum nve0_fifo_sched_reason[] = { static const struct nouveau_enum nve0_fifo_fault_engine[] = { { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, { 0x03, "IFB" }, - { 0x04, "BAR1" }, - { 0x05, "BAR3" }, + { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, + { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, @@ -549,9 +549,10 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); u32 client = (stat & 0x00001f00) >> 8; - const struct nouveau_enum *en; - struct nouveau_engine *engine; + struct nouveau_engine *engine = NULL; struct nouveau_object *engctx = NULL; + const struct nouveau_enum *en; + const char *name = "unknown"; nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo); @@ -567,14 +568,22 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) } if (en && en->data2) { - engine = nouveau_engine(priv, en->data2); - if (engine) - engctx = nouveau_engctx_get(engine, inst); - + if (en->data2 == NVDEV_SUBDEV_BAR) { + nv_mask(priv, 0x001704, 0x00000000, 0x00000000); + name = "BAR1"; + } else + if (en->data2 == NVDEV_SUBDEV_INSTMEM) { + nv_mask(priv, 0x001714, 0x00000000, 0x00000000); + name = "BAR3"; + } else { + engine = nouveau_engine(priv, en->data2); + if (engine) { + engctx = nouveau_engctx_get(engine, inst); + name = nouveau_client_name(engctx); + } + } } - - pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, - nouveau_client_name(engctx)); + pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, name); nouveau_engctx_put(engctx); } |