diff options
| author |   Ben Skeggs <bskeggs@redhat.com> | 2020-06-20 14:21:59 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2020-07-24 18:51:00 +1000 |
| commit | 1070832b1eab7309c59d9564ed26f84932fed817 (patch) | |
| tree | 9f8cfd384b04500e99d6a1b18a2d6dd311a5263b /drivers/gpu/drm/nouveau/dispnv50 | |
| parent | drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_set() (diff) | |
| download | linux-dev-1070832b1eab7309c59d9564ed26f84932fed817.tar.xz linux-dev-1070832b1eab7309c59d9564ed26f84932fed817.zip | |
drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_clr()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/dispnv50')
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/base507c.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index fac830cb9eaa..db811751800a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -56,8 +56,11 @@ base507c_image_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV507C, 0x0084, 0x00000000); - PUSH_NVSQ(push, NV507C, 0x00c0, 0x00000000); + PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL, + NVDEF(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING) | + NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0)); + + PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index a3ab22608f8b..b071cca8dfbf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -127,8 +127,11 @@ wndwc37e_image_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37E, 0x0308, 0x00000000); - PUSH_NVSQ(push, NVC37E, 0x0240, 0x00000000); + PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, + NVVAL(NVC37E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0) | + NVDEF(NVC37E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING)); + + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000); return 0; } |