drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_set()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

5 files changed, 56 insertions, 28 deletions

diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c
index a4759641931f..f46603cc6f01 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c
@@ -270,8 +270,13 @@ head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 	if ((ret = PUSH_WAIT(push, 3)))
 		return ret;
 
-	PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30,
-				0x0844 + (i * 0x400), asyh->olut.offset >> 8);
+	PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
+		  NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
+		  NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
+		  NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
+
+				HEAD_SET_BASE_LUT_HI(i),
+		  NVVAL(NV507D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
 	return 0;
 }
 
@@ -299,9 +304,9 @@ head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 		return false;
 
 	if (asyh->base.cpp == 1)
-		asyh->olut.mode = 0;
+		asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES;
 	else
-		asyh->olut.mode = 1;
+		asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES;
 
 	asyh->olut.load = head507d_olut_load;
 	return true;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c
index 66bacb4bb712..01a8887f4bbe 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c
@@ -24,6 +24,8 @@
 
 #include <nvif/push507c.h>
 
+#include <nvhw/class/cl827d.h>
+
 static int
 head827d_curs_clr(struct nv50_head *head)
 {
@@ -104,9 +106,15 @@ head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 	if ((ret = PUSH_WAIT(push, 5)))
 		return ret;
 
-	PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30,
-				0x0844 + (i * 0x400), asyh->olut.offset >> 8);
-	PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), asyh->olut.handle);
+	PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
+		  NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
+
+				HEAD_SET_BASE_LUT_HI(i),
+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
+
+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c
index 9a0a1ceb5432..69aa24bc7678 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c
@@ -235,9 +235,15 @@ head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 	if ((ret = PUSH_WAIT(push, 5)))
 		return ret;
 
-	PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x80000000 | asyh->olut.mode << 24,
-				0x044c + (i * 0x300), asyh->olut.offset >> 8);
-	PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), asyh->olut.handle);
+	PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
+		  NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |
+		  NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |
+		  NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),
+
+				HEAD_SET_OUTPUT_LUT_HI(i),
+		  NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
+
+	PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
 	return 0;
 }
 
@@ -264,7 +270,11 @@ head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 	if (size != 256 && size != 1024)
 		return false;
 
-	asyh->olut.mode = size == 1024 ? 4 : 7;
+	if (size == 1024)
+		asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
+	else
+		asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
+
 	asyh->olut.load = head907d_olut_load;
 	return true;
 }
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
index e397ababa3e7..eb81ed1e0707 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
@@ -157,11 +157,13 @@ headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 	if ((ret = PUSH_WAIT(push, 4)))
 		return ret;
 
-	PUSH_NVSQ(push, NVC37D, 0x20a4 + (i * 0x400), asyh->olut.output_mode << 8 |
-						      asyh->olut.range << 4 |
-						      asyh->olut.size,
-				0x20a8 + (i * 0x400), asyh->olut.offset >> 8,
-				0x20ac + (i * 0x400), asyh->olut.handle);
+	PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
+		  NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) |
+		  NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) |
+		  NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode),
+
+				HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8,
+				HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle);
 	return 0;
 }
 
@@ -171,10 +173,10 @@ headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 	if (size != 256 && size != 1024)
 		return false;
 
-	asyh->olut.mode = 2;
-	asyh->olut.size = size == 1024 ? 2 : 0;
-	asyh->olut.range = 0;
-	asyh->olut.output_mode = 1;
+	asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 :
+					 NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257;
+	asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY;
+	asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE;
 	asyh->olut.load = head907d_olut_load;
 	return true;
 }
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
index 9cfaf62341b0..9cd4781a52ed 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
@@ -99,12 +99,15 @@ headc57d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 	if ((ret = PUSH_WAIT(push, 5)))
 		return ret;
 
-	PUSH_NVSQ(push, NVC57D, 0x2280 + (i * 0x400), asyh->olut.size << 8 |
-						      asyh->olut.mode << 2 |
-						      asyh->olut.output_mode,
-				0x2284 + (i * 0x400), 0xffffffff,
-				0x2288 + (i * 0x400), asyh->olut.handle,
-				0x228c + (i * 0x400), asyh->olut.offset >> 8);
+	PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
+		  NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) |
+		  NVDEF(NVC57D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |
+		  NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |
+		  NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size),
+
+				HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff,
+				HEAD_SET_CONTEXT_DMA_OLUT(i), asyh->olut.handle,
+				HEAD_SET_OFFSET_OLUT(i), asyh->olut.offset >> 8);
 	return 0;
 }
 
@@ -167,9 +170,9 @@ headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
 	if (size != 0 && size != 256 && size != 1024)
 		return false;
 
-	asyh->olut.mode = 2; /* DIRECT10 */
+	asyh->olut.mode = NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10;
 	asyh->olut.size = 4 /* VSS header. */ + 1024 + 1 /* Entries. */;
-	asyh->olut.output_mode = 1; /* INTERPOLATE_ENABLE. */
+	asyh->olut.output_mode = NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE;
 	if (size == 256)
 		asyh->olut.load = headc57d_olut_load_8;
 	else