diff options
| author |   Ben Skeggs <bskeggs@redhat.com> | 2021-11-23 18:18:06 +1000 |
|---|---|---|
| committer |   Karol Herbst <kherbst@redhat.com> | 2021-12-16 18:46:10 +0100 |
| commit | 70704fbf67ddc07ffc81073a3af1f7b2171697eb (patch) | |
| tree | f087586b114e39baa4f9fd7b54a6c926a42fb3af /drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h | |
| parent | drm/nouveau/disp/dp: add support for hbr3 (diff) | |
| download | linux-dev-70704fbf67ddc07ffc81073a3af1f7b2171697eb.tar.xz linux-dev-70704fbf67ddc07ffc81073a3af1f7b2171697eb.zip | |
drm/nouveau/disp/dp: add support for eDP link rates
eDP 1.4 adds a table of link rates supported by the sink to DPCD, as
well as a LINK_RATE_SET register to select between the entries in it.
If present, we will use this data to generate our internal link rate
table rather than using the standard list based on MAX_LINK_RATE.
Some recent laptops report MAX_LINK_RATE=0, and require this support.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/17
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h index 3b751cd09a16..8e59dd469da6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h @@ -23,8 +23,9 @@ struct nvkm_dp { u8 dpcd[16]; struct { + int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ u32 rate; - } rate[4]; + } rate[8]; int rates; int links; @@ -51,6 +52,8 @@ void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); #define DPCD_RC03_MAX_DOWNSPREAD 0x01 #define DPCD_RC0E 0x0000e #define DPCD_RC0E_AUX_RD_INTERVAL 0x7f +#define DPCD_RC10_SUPPORTED_LINK_RATES(i) 0x00010 +#define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE 16 /* DPCD Link Configuration */ #define DPCD_LC00_LINK_BW_SET 0x00100 @@ -75,6 +78,8 @@ void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 +#define DPCD_LC15_LINK_RATE_SET 0x00115 +#define DPCD_LC15_LINK_RATE_SET_MASK 0x07 /* DPCD Link/Sink Status */ #define DPCD_LS02 0x00202 |