drm/nouveau/gr: cosmetic changes

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 57 insertions, 57 deletions

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 0214e8a91dac..dea1cb907318 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -127,24 +127,24 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	     struct nvkm_oclass *oclass, void *data, u32 size,
 	     struct nvkm_object **pobject)
 {
-	struct nv20_gr_priv *priv;
+	struct nv20_gr *gr;
 	int ret;
 
-	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
+	*pobject = nv_object(gr);
 	if (ret)
 		return ret;
 
-	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
-			      NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
+			      NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
 	if (ret)
 		return ret;
 
-	nv_subdev(priv)->unit = 0x00001000;
-	nv_subdev(priv)->intr = nv20_gr_intr;
-	nv_engine(priv)->cclass = &nv30_gr_cclass;
-	nv_engine(priv)->sclass = nv30_gr_sclass;
-	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
+	nv_subdev(gr)->unit = 0x00001000;
+	nv_subdev(gr)->intr = nv20_gr_intr;
+	nv_engine(gr)->cclass = &nv30_gr_cclass;
+	nv_engine(gr)->sclass = nv30_gr_sclass;
+	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
 	return 0;
 }
 
@@ -152,68 +152,68 @@ int
 nv30_gr_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
-	struct nv20_gr_priv *priv = (void *)engine;
+	struct nv20_gr *gr = (void *)engine;
 	struct nvkm_fb *fb = nvkm_fb(object);
 	int ret, i;
 
-	ret = nvkm_gr_init(&priv->base);
+	ret = nvkm_gr_init(&gr->base);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
-
-	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
-	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
-
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
-	nv_wr32(priv, 0x400890, 0x01b463ff);
-	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
-	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
-	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
-	nv_wr32(priv, 0x400B80, 0x1003d888);
-	nv_wr32(priv, 0x400B84, 0x0c000000);
-	nv_wr32(priv, 0x400098, 0x00000000);
-	nv_wr32(priv, 0x40009C, 0x0005ad00);
-	nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
-	nv_wr32(priv, 0x4000a0, 0x00000000);
-	nv_wr32(priv, 0x4000a4, 0x00000008);
-	nv_wr32(priv, 0x4008a8, 0xb784a400);
-	nv_wr32(priv, 0x400ba0, 0x002f8685);
-	nv_wr32(priv, 0x400ba4, 0x00231f3f);
-	nv_wr32(priv, 0x4008a4, 0x40000020);
-
-	if (nv_device(priv)->chipset == 0x34) {
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
-		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
-		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
+	nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
+
+	nv_wr32(gr, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
+	nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
+
+	nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+	nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
+	nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0);
+	nv_wr32(gr, 0x400890, 0x01b463ff);
+	nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
+	nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000);
+	nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
+	nv_wr32(gr, 0x400B80, 0x1003d888);
+	nv_wr32(gr, 0x400B84, 0x0c000000);
+	nv_wr32(gr, 0x400098, 0x00000000);
+	nv_wr32(gr, 0x40009C, 0x0005ad00);
+	nv_wr32(gr, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
+	nv_wr32(gr, 0x4000a0, 0x00000000);
+	nv_wr32(gr, 0x4000a4, 0x00000008);
+	nv_wr32(gr, 0x4008a8, 0xb784a400);
+	nv_wr32(gr, 0x400ba0, 0x002f8685);
+	nv_wr32(gr, 0x400ba4, 0x00231f3f);
+	nv_wr32(gr, 0x4008a4, 0x40000020);
+
+	if (nv_device(gr)->chipset == 0x34) {
+		nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+		nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00200201);
+		nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
+		nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000008);
+		nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+		nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000032);
+		nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
+		nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000002);
 	}
 
-	nv_wr32(priv, 0x4000c0, 0x00000016);
+	nv_wr32(gr, 0x4000c0, 0x00000016);
 
 	/* Turn all the tiling regions off. */
 	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
-	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
-	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
-	nv_wr32(priv, 0x0040075c             , 0x00000001);
+	nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+	nv_wr32(gr, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
+	nv_wr32(gr, 0x0040075c             , 0x00000001);
 
 	/* begin RAM config */
-	/* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
-	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
-	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
-	if (nv_device(priv)->chipset != 0x34) {
-		nv_wr32(priv, 0x400750, 0x00EA0000);
-		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
-		nv_wr32(priv, 0x400750, 0x00EA0004);
-		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
+	/* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
+	nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200));
+	nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204));
+	if (nv_device(gr)->chipset != 0x34) {
+		nv_wr32(gr, 0x400750, 0x00EA0000);
+		nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100200));
+		nv_wr32(gr, 0x400750, 0x00EA0004);
+		nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100204));
 	}
 	return 0;
 }