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| author |   Alex Deucher <alexander.deucher@amd.com> | 2011-11-17 14:57:50 -0500 |
|---|---|---|
| committer |   Dave Airlie <airlied@redhat.com> | 2011-12-20 19:51:54 +0000 |
| commit | b40e7e1608c332767e6b94bed7af84b30418e739 (patch) | |
| tree | deedf98f2830500cd5fb524c07ed21fc1fc6c57c /drivers/gpu/drm/radeon/nid.h | |
| parent | drm/radeon/kms: add some new ring params to better handle other ring types (diff) | |
| download | linux-dev-b40e7e1608c332767e6b94bed7af84b30418e739.tar.xz linux-dev-b40e7e1608c332767e6b94bed7af84b30418e739.zip | |
drm/radeon/kms: add cayman specific fence_ring_emit
cayman is wb only and doesn't have a VC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/nid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/nid.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 4672869cdb26..e8d8124834b3 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -411,6 +411,10 @@ #define CP_ME_RAM_DATA 0xC160 #define CP_DEBUG 0xC1FC +#define VGT_EVENT_INITIATOR 0x28a90 +# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) +# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) + /* * PM4 */ @@ -494,7 +498,27 @@ #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) #define PACKET3_COND_WRITE 0x45 #define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + * 5 - TS events + */ #define PACKET3_EVENT_WRITE_EOP 0x47 +#define DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit counter value + */ +#define INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ #define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_PREAMBLE_CNTL 0x4A # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |