diff options
| author |   Chris Zhong <zyw@rock-chips.com> | 2017-03-22 09:54:51 +0800 |
|---|---|---|
| committer |   Sean Paul <seanpaul@chromium.org> | 2017-03-24 14:48:58 -0400 |
| commit | 395eaaae1ddd4c6ad0c88bdff65184ef3c861647 (patch) | |
| tree | 8ed66313ade2529a398cef7695a512ee959aa460 /drivers/gpu/drm/rockchip/dw-mipi-dsi.c | |
| parent | drm/rockchip/dsi: enable the grf clk before writing grf registers (diff) | |
| download | linux-dev-395eaaae1ddd4c6ad0c88bdff65184ef3c861647.tar.xz linux-dev-395eaaae1ddd4c6ad0c88bdff65184ef3c861647.zip | |
drm/rockchip/dsi: correct the grf_switch_reg name
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1490147691-4489-5-git-send-email-zyw@rock-chips.com
Diffstat (limited to 'drivers/gpu/drm/rockchip/dw-mipi-dsi.c')
| -rw-r--r-- | drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 6a017be99557..21b9737662ae 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -34,7 +34,7 @@ #define RK3288_DSI0_SEL_VOP_LIT BIT(6) #define RK3288_DSI1_SEL_VOP_LIT BIT(9) -#define RK3399_GRF_SOC_CON19 0x6250 +#define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_DSI0_SEL_VOP_LIT BIT(0) #define RK3399_DSI1_SEL_VOP_LIT BIT(4) @@ -1151,7 +1151,7 @@ static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = { static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT, .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT, - .grf_switch_reg = RK3399_GRF_SOC_CON19, + .grf_switch_reg = RK3399_GRF_SOC_CON20, .grf_dsi0_mode = RK3399_GRF_DSI_MODE, .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, |