diff options
| author |   Mark yao <mark.yao@rock-chips.com> | 2017-07-26 14:19:12 +0800 |
|---|---|---|
| committer | Mark Yao <mark.yao@rock-chips.com> | 2017-07-31 08:43:57 +0800 |
| commit | 9548e1b49a0cb2eb0cec1cf2560c920fe2954608 (patch) | |
| tree | 8f9904575fe6612cd0a46b313316d8a68bad64de /drivers/gpu/drm/rockchip/rockchip_drm_vop.c | |
| parent | drm/rockchip: vop: initialize registers directly (diff) | |
| download | linux-dev-9548e1b49a0cb2eb0cec1cf2560c920fe2954608.tar.xz linux-dev-9548e1b49a0cb2eb0cec1cf2560c920fe2954608.zip | |
drm/rockchip: vop: move write_relaxed flags to vop register
Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
cfg_done, standby and interrupt related register.
All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501049953-5946-1-git-send-email-mark.yao@rock-chips.com
Diffstat (limited to 'drivers/gpu/drm/rockchip/rockchip_drm_vop.c')
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 28 |
1 files changed, 11 insertions, 17 deletions
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index cbc79cb9feaa..11f0b21bce22 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -42,33 +42,27 @@ #include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ - vop_mask_write(x, off, mask, shift, v, write_mask, true) - -#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ - vop_mask_write(x, off, mask, shift, v, write_mask, false) - -#define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, \ - reg.mask, reg.shift, v, reg.write_mask) -#define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, \ - mask, reg.shift, v, reg.write_mask) +#define REG_SET(x, base, reg, v) \ + vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \ + v, reg.write_mask, reg.relaxed) +#define REG_SET_MASK(x, base, reg, mask, v) \ + vop_mask_write(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask, reg.relaxed) #define VOP_WIN_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->name, v, RELAXED) + REG_SET(x, win->base, win->phy->name, v) #define VOP_SCL_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) + REG_SET(x, win->base, win->phy->scl->name, v) #define VOP_SCL_SET_EXT(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) + REG_SET(x, win->base, win->phy->scl->ext->name, v) #define VOP_CTRL_SET(x, name, v) \ - REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) + REG_SET(x, 0, (x)->data->ctrl->name, v) #define VOP_INTR_GET(vop, name) \ vop_read_reg(vop, 0, &vop->data->ctrl->name) #define VOP_INTR_SET(vop, name, mask, v) \ - REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) + REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v) #define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ int i, reg = 0, mask = 0; \ |