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| author |   Chen-Yu Tsai <wens@csie.org> | 2018-03-15 19:41:31 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2018-03-19 15:37:21 +0100 |
| commit | 6664e9dc5383a6e2998fffa41bb697517de57622 (patch) | |
| tree | 3e99956490e19d75b08b84b6c22ddb3f78897061 /drivers/gpu/drm/sun4i/sun4i_tcon.h | |
| parent | drm/sun4i: Add DT binding for Detail Enhancement Unit in Allwinner A80 SoC (diff) | |
| download | linux-dev-6664e9dc5383a6e2998fffa41bb697517de57622.tar.xz linux-dev-6664e9dc5383a6e2998fffa41bb697517de57622.zip | |
drm/sun4i: Add support for A80 TCONs
The Allwinner A80 SoC has 2 documented TCONs. The display pipeline
diagram from the user manual shows a third TCON, but it's missing
an interrupt line, and its registers are not explained either.
It's also not used in Allwinner's vendor BSP.
The first TCON only has channel 0, for LCD panel output. The TCON
hardware setup is peculiar in that the eDP reset must also be
deasserted to allow access to the TCON. How the eDP module is wired
in the SoC itself is never explained.
The second TCON only has channel 1, and its output is connected to
the HDMI encoder block.
This patch adds a "needs_edp_reset" field to the tcon quirks structure,
and adds quirks and compatible strings for the 2 documented TCONs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180315114136.24747-4-wens@csie.org
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun4i_tcon.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index 78d55e7cd2b3..d3a945b7bb60 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -176,6 +176,7 @@ struct sun4i_tcon_quirks { bool has_channel_1; /* a33 does not have channel 1 */ bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */ bool needs_de_be_mux; /* sun6i needs mux to select backend */ + bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ /* callback to handle tcon muxing options */ int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); |