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| author |   Thierry Reding <treding@nvidia.com> | 2015-07-07 21:01:26 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:52 +0100 |
| commit | ad7f2dda38911698deb2cc9ea45362f9a127e3f4 (patch) | |
| tree | 5abfecdb2db327c54ce5bb7a47d7694af9350a48 /drivers/gpu/drm/tegra/dp.h | |
| parent | drm/tegra: dp: Read eDP version from DPCD (diff) | |
| download | linux-dev-ad7f2dda38911698deb2cc9ea45362f9a127e3f4.tar.xz linux-dev-ad7f2dda38911698deb2cc9ea45362f9a127e3f4.zip | |
drm/tegra: dp: Read AUX read interval from DPCD
Store the AUX read interval from DPCD, so that it can be used to wait
for the durations given in the specification during link training.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 681cbd0a0094..1fe2d4f45ba3 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) + * @aux_rd_interval: AUX read interval to use for training (in microseconds) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes @@ -70,6 +71,16 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; + + /** + * @cr: clock recovery read interval + * @ce: channel equalization read interval + */ + struct { + unsigned int cr; + unsigned int ce; + } aux_rd_interval; + unsigned char edp; unsigned int rate; |