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| author |   Thierry Reding <treding@nvidia.com> | 2015-01-28 16:32:52 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-02 18:49:23 +0200 |
| commit | 5c1c071a3667600d1b8426dba031b2d4a20a3efa (patch) | |
| tree | 144ef5ced455205b60db36fb46660739ffb82d84 /drivers/gpu/drm/tegra/hdmi.c | |
| parent | drm/tegra: hdmi: Resets are synchronous (diff) | |
| download | linux-dev-5c1c071a3667600d1b8426dba031b2d4a20a3efa.tar.xz linux-dev-5c1c071a3667600d1b8426dba031b2d4a20a3efa.zip | |
drm/tegra: hdmi: Name register fields consistently
Name the fields of the SOR_SEQ_CTL register consistently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 05213b2ec2bd..06ab1783bba1 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -952,7 +952,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, } tegra_hdmi_writel(hdmi, - SOR_SEQ_CTL_PU_PC(0) | + SOR_SEQ_PU_PC(0) | SOR_SEQ_PU_PC_ALT(0) | SOR_SEQ_PD_PC(8) | SOR_SEQ_PD_PC_ALT(8), |