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| author |   Shawn Guo <shawn.guo@linaro.org> | 2017-01-12 22:20:31 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2017-01-28 11:51:22 +0800 |
| commit | 9cc2a68519aeac42775161a4131d91120f3a927e (patch) | |
| tree | e8b439205ffd2a66664678c2c4c190aa4ad8393f /drivers/gpu/drm/zte/zx_vou_regs.h | |
| parent | drm: zte: move struct vou_inf into zx_vou driver (diff) | |
| download | linux-dev-9cc2a68519aeac42775161a4131d91120f3a927e.tar.xz linux-dev-9cc2a68519aeac42775161a4131d91120f3a927e.zip | |
drm: zte: add function to configure vou_ctrl dividers
The clock control module (CRM) cannot always provide desired frequency
for all VOU output devices. That's why VOU integrates a few dividers
to further divide the clocks from CRM. Let's add an interface for
configuring these dividers.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/zte/zx_vou_regs.h')
| -rw-r--r-- | drivers/gpu/drm/zte/zx_vou_regs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h index ae5cbce2a7a1..c066ef123434 100644 --- a/drivers/gpu/drm/zte/zx_vou_regs.h +++ b/drivers/gpu/drm/zte/zx_vou_regs.h @@ -176,11 +176,27 @@ #define VOU_INF_DATA_SEL 0x08 #define VOU_SOFT_RST 0x14 #define VOU_CLK_SEL 0x18 +#define VGA_AUX_DIV_SHIFT 29 +#define VGA_MAIN_DIV_SHIFT 26 +#define PIC_MAIN_DIV_SHIFT 23 +#define PIC_AUX_DIV_SHIFT 20 #define VOU_CLK_VL2_SEL BIT(8) #define VOU_CLK_VL1_SEL BIT(7) #define VOU_CLK_VL0_SEL BIT(6) #define VOU_CLK_GL1_SEL BIT(5) #define VOU_CLK_GL0_SEL BIT(4) +#define VOU_DIV_PARA 0x1c +#define DIV_PARA_UPDATE BIT(31) +#define TVENC_AUX_DIV_SHIFT 28 +#define HDMI_AUX_PNX_DIV_SHIFT 25 +#define HDMI_MAIN_PNX_DIV_SHIFT 22 +#define HDMI_AUX_DIV_SHIFT 19 +#define HDMI_MAIN_DIV_SHIFT 16 +#define TVENC_MAIN_DIV_SHIFT 13 +#define INF_AUX_DIV_SHIFT 9 +#define INF_MAIN_DIV_SHIFT 6 +#define LAYER_AUX_DIV_SHIFT 3 +#define LAYER_MAIN_DIV_SHIFT 0 #define VOU_CLK_REQEN 0x20 #define VOU_CLK_EN 0x24 #define VOU_INF_HDMI_CTRL 0x30 |