diff options
| author |   Thierry Reding <treding@nvidia.com> | 2015-07-07 20:59:22 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:45 +0100 |
| commit | 7aa3cc540d00b0be7d225202fa5c2d0c8e99f3f1 (patch) | |
| tree | 66f1a627897d4ca88ebedc7937b54ad54b2e3ccc /drivers/gpu/drm | |
| parent | drm/tegra: dp: Read alternate scrambler reset capability from sink (diff) | |
| download | linux-dev-7aa3cc540d00b0be7d225202fa5c2d0c8e99f3f1.tar.xz linux-dev-7aa3cc540d00b0be7d225202fa5c2d0c8e99f3f1.zip | |
drm/tegra: dp: Read eDP version from DPCD
If the sink supports eDP, read the eDP revision from it's DPCD.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.h | 2 |
2 files changed, 18 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 1f48c2190e3b..2be0a47ecbec 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -5,9 +5,12 @@ */ #include <drm/drm_dp_helper.h> +#include <drm/drm_print.h> #include "dp.h" +static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 }; + static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; @@ -37,6 +40,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->max_lanes = 0; drm_dp_link_caps_reset(&link->caps); + link->edp = 0; link->rate = 0; link->lanes = 0; @@ -55,7 +59,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) */ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { - u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u8 dpcd[DP_RECEIVER_CAP_SIZE], value; int err; drm_dp_link_reset(link); @@ -73,9 +77,19 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); - if (drm_dp_alternate_scrambler_reset_cap(dpcd)) + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { link->caps.alternate_scrambler_reset = true; + err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value); + if (err < 0) + return err; + + if (value >= ARRAY_SIZE(drm_dp_edp_revisions)) + DRM_ERROR("unsupported eDP version: %02x\n", value); + else + link->edp = drm_dp_edp_revisions[value]; + } + link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 45e8ff18ab6a..681cbd0a0094 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) + * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes */ @@ -69,6 +70,7 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; + unsigned char edp; unsigned int rate; unsigned int lanes; |