diff options
| author |   Alexander Stein <alexander.stein@informatik.tu-chemnitz.de> | 2013-05-20 19:14:00 +0200 |
|---|---|---|
| committer |   Ben Skeggs <bskeggs@redhat.com> | 2013-06-05 14:02:40 +1000 |
| commit | beba44b17d572ebb4909c1327360918ee4d89e43 (patch) | |
| tree | 8f611127c18fc4d0092e810b65491da95795d8a4 /drivers/gpu/drm | |
| parent | drm/nouveau: ensure channels are stopped before saving fences for suspend (diff) | |
| download | linux-dev-beba44b17d572ebb4909c1327360918ee4d89e43.tar.xz linux-dev-beba44b17d572ebb4909c1327360918ee4d89e43.zip | |
drm/nv84/disp: Fix HDMI audio regression
Code refactoring in commit 8e9e3d2deacc460fbb8a4691140318f6e85e6891
(drm/nv84/disp: move hdmi control into core) disabled HDMI audio on my
nv84 by removing too much old code without adding it in the new one.
This patch adds the missing code within the new code layout resulting in
HDMI audio working again.
It should work on any HDMI head, but due to lacking ahrdware I could
only test the (1st) one.
It also might be possible that similar code is needed for nva3, which I
can't test.
Signed-off-by: Alexander Stein <alexander.stein@informatik.tu-chemnitz.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c index 0d36bdc51417..7fdade6e604d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c @@ -55,6 +55,10 @@ nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) nv_wr32(priv, 0x616510 + hoff, 0x00000000); nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); + nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + /* ??? */ nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ |