diff options
| author |   Sean Paul <seanpaul@chromium.org> | 2014-09-10 10:52:03 -0400 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2014-11-13 16:11:51 +0100 |
| commit | 26f7a92a3a275cad7b0f39063e8cd92e002aff1a (patch) | |
| tree | 5af76373db2acb8b581419e100dcedbbd75f9688 /drivers/gpu/host1x | |
| parent | gpu: host1x: mipi: Registers are 32 bits wide (diff) | |
| download | linux-dev-26f7a92a3a275cad7b0f39063e8cd92e002aff1a.tar.xz linux-dev-26f7a92a3a275cad7b0f39063e8cd92e002aff1a.zip | |
gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL
By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE
("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the
description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states
that if the value of the prescale is 0 (or 0.1us), the filter should be
set between 2-5. However, the current code sets it to 0.
For now, let's keep the prescale and filter values as-is, which is most
likely the power-on-reset values of 0x2 and 0xa, respectively.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/host1x')
| -rw-r--r-- | drivers/gpu/host1x/mipi.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index a3e215a0116f..0d8c3ae8db6a 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -208,7 +208,9 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) tegra_mipi_writel(device->mipi, value, modules[i].reg); } - tegra_mipi_writel(device->mipi, MIPI_CAL_CTRL_START, MIPI_CAL_CTRL); + value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); + value |= MIPI_CAL_CTRL_START; + tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); err = tegra_mipi_wait(device->mipi); |