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| author |   Zhao Yan <yan.y.zhao@intel.com> | 2017-02-28 15:41:03 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-03-01 10:12:36 +0800 |
| commit | 1f58af304cce9e4a25b62b3619e69c586203c8ca (patch) | |
| tree | b47a4a1f14b63fcbb9a952b15e062b05b3acc91f /drivers/gpu | |
| parent | drm/i915/gvt: add more registers into handlers list (diff) | |
| download | linux-dev-1f58af304cce9e4a25b62b3619e69c586203c8ca.tar.xz linux-dev-1f58af304cce9e4a25b62b3619e69c586203c8ca.zip | |
drm/i915/gvt: fix an error for one register
register 0x20e0 should be mode register
v2: rebased to latest code base
Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index ef17c38e00c4..548aedfbd402 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2749,7 +2749,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); MMIO_D(0xd08, D_SKL); - MMIO_D(0x20e0, D_SKL); + MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL); MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); /* TRTT */ |