diff options
| author |   Eric Yang <Eric.Yang2@amd.com> | 2017-07-12 18:38:04 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:08 -0400 |
| commit | 71a2f23e9101887de251ef1dcd35219d4e4f5e93 (patch) | |
| tree | 51885c1e4ff2746e0ca2103f2f3096b17c9326f9 /drivers/gpu | |
| parent | drm/amd/display: ensure OTG is locked before proceeding (diff) | |
drm/amd/display: fix mpo exit hang
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 82a96de2843f..dbf9cea2e418 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -500,8 +500,10 @@ static void reset_front_end( HUBP_CLOCK_ENABLE, 0); REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); + + if (mpcc_cfg.top_of_tree) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); xfm->funcs->transform_reset(xfm); @@ -1584,7 +1586,7 @@ static void dcn10_apply_ctx_for_surface( int i; /* reset unused mpcc */ - /*for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; @@ -1593,7 +1595,12 @@ static void dcn10_apply_ctx_for_surface( || (!pipe_ctx->stream && old_pipe_ctx->stream)) { struct mpcc_cfg mpcc_cfg; - mpcc_cfg.opp_id = 0xf; + if (!old_pipe_ctx->top_pipe) { + ASSERT(0); + continue; + } + + mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe; @@ -1607,7 +1614,7 @@ static void dcn10_apply_ctx_for_surface( "Reset mpcc for pipe %d\n", old_pipe_ctx->pipe_idx); } - }*/ + } if (!surface) return; |