diff options
| author |   José Roberto de Souza <jose.souza@intel.com> | 2019-10-25 17:13:21 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-10-29 12:12:47 -0700 |
| commit | 7a40aac1d77ab05ca375ac34de44e7972cc61dc3 (patch) | |
| tree | 18ef4d05c726242dd94f2d287b78e0af823d3bf5 /drivers/gpu | |
| parent | drm/i915/display: Handle fused off HDCP (diff) | |
| download | linux-dev-7a40aac1d77ab05ca375ac34de44e7972cc61dc3.tar.xz linux-dev-7a40aac1d77ab05ca375ac34de44e7972cc61dc3.zip | |
drm/i915/display: Check if FBC is fused off
Check if FBC is fused off and handle it.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-3-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_device_info.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d90adf02e0a5..ecbcc0e33850 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7743,6 +7743,7 @@ enum { #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) #define SKL_DFSM _MMIO(0x51000) +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index e7dd6092c105..a3e90714cfa2 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -984,6 +984,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) info->display.has_hdcp = 0; + + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) + info->display.has_fbc = 0; } /* Initialize slice/subslice/EU info */ |